The present invention relates to computer systems, and more particularly, to soft post package repair function validation for a memory device.
Memory subsystems may make use of multiple types of error checking, correction and reporting mechanisms to improve recoverability, availability, and serviceability (RAS) and data integrity. In higher-end systems, such as mainframes, it is typical for data to be checked, corrected and reported upon in many places within write and read paths. The write and read paths can include checking, correction and reporting from a memory control to a physical memory interface through chip packaging, board routing across a board into a memory device, and return paths. As memory technology has evolved, the amount of checking, correction, and reporting included in memory subsystems has expanded to enable higher speed and higher density technologies.
Soft Post Package Repair (sPPR) provides a function in a memory device to quickly, but temporarily, repair a row element in a bank group on some types of memory devices by using a spare row of the memory device. One sPPR is allowed per bank group for some types of memory devices, such as a double-data rate fourth-generation (DDR4) dynamic random access memory (DRAM) device. If more than one sPPR request is made to the same bank group, the most recent sPPR address replaces the earlier issued address. Invalid deployment of sPPR or an out-of-specification design of a memory device can lead to memory device traffic not being diverted to the spare row of the memory device.